Tensilica introduces imaging and video dataplane processor

Tensilica, Inc., a provider of low-power processors used for embedded control and digital signal processing, has introduced IVP, an imaging and video dataplane processor, or DPU, that is ideal for the image/video signal processing functions in mobile handsets, tablets, digital televisions, or DTV, automotive, video games and computer vision based applications.

IVP is supported by a network of third-party application developers who are actively porting image applications to the IVP platform including multi-frame image capture and video pre- and post-processing algorithms, as well as established, yet evolving, technologies such as video stabilization, high dynamic range (HDR) image, video HDR, object and face recognition and tracking, low-light image enhancement, digital zoom and gesture recognition, the company said.

According to the company, with its unique architecture tuned for imaging and video pixel processing that gives it peak performance of 10 to 20x most host CPUs, the IVP is capable of over 130 billion 16-bit RISC-equivalent operations per second. This allows IVP to tackle the complexity of new image, gesture and video algorithms which would be impossible to run on general-purpose host CPU architectures. It also provides 2 to 4x the performance of any merchant imaging DSP IP core.

"Consumers want advanced imaging functions like HDR, but the shot-to-shot time with the current technology is several seconds, which is way too long. Users want it to work 50x faster. We can give consumers the instant-on, high-quality image and video capture they want," stated Chris Rowen, Tensilica's founder and CTO. "The IVP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing, supporting increasing sensor resolutions. It is ideal for tomorrow's exciting new products."

Tensilica's IVP is based on a 4-way VLIW (very long instruction word) architecture that delivers high parallelism intermixed with code-compact instructions, with a 32-way vector SIMD (single instruction, multiple data) dataset. The architecture includes an integrated DMA (direct memory access) transfer engine with up to 10 GBytes/second of throughput and local memory throughput of 1024 bits per cycle (sixty-four 16-bit pixels/cycle) to keep up with the pace of resolution and frame rate requirements.

Tensilica's IVP DPU can be further customized using Tensilica's patented processor-generation system. The DPU creation process is totally automated and fully supported by a matching software tool chain. The tool chain includes an optimized compiler, linker, assembler and debugger, plus a matching fast instruction set simulator, the company added.