Cadence Design Systems, Inc., a provider of electronic design automation, software, hardware, and silicon intellectual property, has announced the availability of Virtuoso Advanced Node, a new set of custom/analog capabilities designed for the technology nodes of 20 nanometers and below.
Built on the Cadence Virtuoso custom/analog technology, Virtuoso Advanced Node reportedly features capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power consumer electronics devices, the company said.
The new Virtuoso technologies integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) - a foundry-qualified technology for signoff DRC and DPT checking - to conduct on-the-fly checks that reduce layout iterations.
"As a semiconductor leader, we have moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design," said Pierre Dautriche, senior director at STMicroelectronics. "The new Virtuoso advanced-node capabilities have contributed to our transition by providing high-quality automation for our custom/analog chips. Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20 nanometers and ensures a much more efficient development cycle."
Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end. It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.
When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time. By methodically building and checking the design, the designer should eliminate massive 'rip ups' and 'reroutes' that can be found at the end if the circuit wasn't checked along the way, the company added.
Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.